MT48LC8M16A2P-6A:L

MT48LC8M16A2P-6A:L is a SDR SDRAM. The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks are organized as 4096 rows by 2048 columns by 4bits. Each of the x8’s 33,554,432-bit banks are organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks are organized as 4096 rows by 512 columns by 16 bits. The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Timing – cycle time : 6ns at CL = 3 (x16 only)
• 8 Meg x 16 architecture
• 54-pin TSOP II (400 mil) package
• Commercial operating temperature range from 0°C to 70°C