MT48H32M16LFB4-75 IT:C

The 512Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1K columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits. In the reduced page size option, each of the x32’s 134,217,728-bit banks is organized as 16,384 rows by 256 columns by 32 bits. Mobile LPSDR offers substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

• VDD/VDDQ = 1.7-1.95V
• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continuous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive strength (DS)
• 64ms refresh period; 32ms for automotive temperature