MT48H16M32LFB5-6 IT:C

MT48H16M32LFB5-6 IT:C is a mobile LPSDR SDRAM. It is a high-speed CMOS, dynamic random-access memory containing 536,870,912bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). This mobile LPSDR offers substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

• 1.8V/1.8V operating voltage, 16 Meg x 32 configuration
• Standard addressing, 6ns, tCK CL = 3 cycle time
• Fully synchronous : all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Four internal banks for concurrent operation, selectable output drive strength (DS)
• Auto precharge, includes concurrent auto precharge, auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs, on-chip temperature sensor to control self refresh rate
• Partial-array self refresh (PASR), deep power-down (DPD)
• Industrial operating temperature range from -40°C to +85°C, package style is 90-ball VFBGA