MT47H256M8EB-25E:C

MT47H256M8EB-25E:C is a DDR2 SDRAM. It uses a uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially for 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE operation for the DDR2 SDRAM consists of a single 4n-bitwide, two-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. It has JEDEC-standard of 1.8V I/O (SSTL_18-compatible) with differential data strobe (DQS, DQS#) option.

• Operating voltage range is –1.0V to 2.3V(VDD)
• 256Meg x 8 configuration, duplicate output strobe (RDQS) option for x8
• Packaging style is 60-ball 9.0mm x 11.5mm FBGA
• Timing (cycle time) is 2.5ns at CL = 5 (DDR2-800)
• Operating temperature range is 0°C to +85°C
• Data rate is 800MT/s, differential data strobe (DQS, DQS#) option
• DLL to align DQ and DQS transitions with CK, 8 internal banks for concurrent operation
• Programmable CAS latency (CL), WRITE latency = READ latency is 1áµ—CK
• Adjustable data-output drive strength, on-die termination (ODT)
• Supports JEDEC clock jitter specification