MT46V64M8CY-5B:J

MT46V64M8CY-5B:J is a double data rate (DDR) SDRAM. It uses a double data rate architecture to achieve high-speed operation. This double data rate architecture is essentially for 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the memory consists of a single 2n-bit-wide, one-clock cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. It has an internal, pipelined double-data-rate (DDR) architecture with two data accesses per clock cycle.

• Operating voltage range is 2.5V to 2.7V
• 64Meg x 8 configuration
• Packaging style is 8mm x 12.5mm FBGA
• Timing (cycle time) is 5ns at CL = 3 (DDR400)
• Operating temperature range is 0°C to +70°C
• Clock rate is 200MHz, ?RAS lockout supported (?RAP = ?RCD)
• Differential clock inputs (CK and CK#), four internal banks for concurrent operation
• Commands entered on each positive CK edge, concurrent auto precharge option is supported
• DQS edge-aligned with data for READs, centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK, auto refresh 64ms, 8192-cycle