MT46H16M32LFB5-6 AIT:C

The 512Mb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’s 134,217,728- bit banks are organized as 16,384 rows by 256 columns by 32 bits.

• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh, 32ms for automotive temperature