MT44K64M18RB-093E:A

The 1Gb Micron Twin Die RLDRAM 3 is a high-speed memory device designed for high-bandwidth data storage—telecommunications, networking, cache applications, and so forth. Both the x18 and x36 configurations are composed of two 16-bank 576Mb RLDRAM 3 x18 devices. The Twin Die x18 RLDRAM 3 is a 2-rank device that shares address, control, and data signals between both die in the package. Separate CS# pins enable each of the ranks within the package. The Twin Die x36 RLDRAM 3 is a single-rank device that shares command, address, and control signals, but not the data bus. The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output data is referenced to the READ strobes. Commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is programmable to 2, 4, or 8 by a setting in the mode register. The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V supply is used for an internal supply. Bank-scheduled refresh is supported, with the row address generated internally. The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates.

• Uses 576Mb Micron RLDRAM 3 die
• Organization
  • 32 Meg x 18 x 2 ranks
  • 32 Meg x 36 x 1 rank
  • 16 banks per die
  • Common I/O (CIO)
• 1.2V center-terminated push/pull I/O
• 2.5V VEXT, 1.35V VDD, 1.2V VDDQ I/O