MT44K16M36RB-107E:B

The Micron RLDRAM 3 is a high-speed memory device designed for high-bandwidth data storage—telecommunications, networking, cache applications, and so forth. The chip’s 16-bank architecture is optimized for sustainable high-speed operation. The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output data is referenced to the READ strobes. Commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is programmable to 2, 4, or 8 by a setting in the mode register. The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V supply is used for an internal supply. Bank-scheduled refresh is supported with the row address generated internally. The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates.

• 1066 MHz DDR operation (2133 Mb/s/ball data rate)
• 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock frequency)
• Organization
  • 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
  • 16 banks
• 1.2V center-terminated push/pull I/O
• 2.5V VEXT, 1.35V VDD, 1.2V VDDQ I/O
• Reduced cycle time (tRC (MIN) = 8 - 12ns)
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and burst length
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Free-running differential input data clocks (DKx, DKx#) and output data clocks (QKx, QKx#)
• On-die DLL generates CK edge-aligned data and differential output data clock signals
• 64ms refresh (128K refresh per 64ms)
• 168-ball FBGA package
• 40O or 60O matched impedance outputs
• Integrated on-die termination (ODT)
• Single or multibank writes
• Extended operating range (200–1066 MHz)
• READ training