MT42L64M64D2KH-25 IT:A

The 2Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic random-access memory containing 2,147,483,648 bits. The LPDDR2-S4 device is internally configured as an eight-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 16,384 rows by 512 columns by 32 bits.

• Ultra low-voltage core and I/O power supplies
  • VDD2 = 1.14–1.30V
  • VDDCA/VDDQ = 1.14–1.30V
  • VDD1 = 1.70–1.95V
• Clock frequency range
  • 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging