MT41K512M8DA-107:P TR
DRAM Chip DDR3L SDRAM 4G-bit 512Mx8 1.35V 78-Pin F-BGA T/R
- VDD = VDDQ = 1.35V (1.283–1.45V)
- Backward compatible to VDD = VDDQ = 1.5V ±0.075V
- Supports DDR3L devices to be backward compatible in 1.5V applications
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
- Programmable CAS (READ) latency (CL)
- Programmable posted CAS additive latency (AL)
- Programmable CAS (WRITE) latency (CWL)
- Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
- Selectable BC4 or BL8 on-the-fly (OTF)
- Self refresh mode
- TC of 0°C to +95°C
- 64ms, 8192-cycle refresh at 0°C to +85°C
- 32ms at +85°C to +95°C
- Self refresh temperature (SRT)
- Automatic self refresh (ASR)
- Write leveling
- Multipurpose register
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 16 Bit | ||
| 8 Bit | ||
| 4 Gbit | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 933 MHz | ||
| 70 mA | ||
| Surface Mount | ||
| 8 | ||
| 8 Bit | ||
| 8 Bit | ||
| 3.3000 V | ||
| 0 to 95 °C | ||
| 512M x 8 | ||
| 78F-BGA | ||
| 78 | ||
| 9 x 10.5 x 0.85 mm | ||
| Commercial | ||
| FBGA | ||
| DDR3L SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | PROJECTED FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320028 |
| Schedule B: | 8542320060 |
Factory Lead Time: