MT41J128M16JT-125:K TR
DRAM Chip Mobile LPDDR2 SDRAM 2G-Bit 128Mx32 1.8V 168-Pin F-BGA T/R
This is a DDR3 SDRAM Reduced tFAW Addendum. MT41J128M16 – 16 Meg x 16 x 8 Banks device.
- VDD = VDDQ = 1.5V ±0.075V
- 1.5V center-terminated push/pull I/O
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
- Programmable CAS READ latency (CL)
- Posted CAS additive latency (AL)
- Programmable CAS WRITE latency (CWL) based on tCK
- Fixed burst length (BL) of 8 and burst chop (BC) of 4(via the mode register set [MRS])
- Selectable BC4 or BL8 on-the-fly (OTF)
- Self refresh mode
- TC of 0°C to 95°C
- 64ms, 8192 cycle refresh at 0°C to 85°C
- 32ms, 8192 cycle refresh at 85°C to 95°C
- Self refresh temperature (SRT)
- Write leveling
- Multipurpose register
- Output driver calibration
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 17 Bit | ||
| 800 MHz | ||
| 16 Bit | ||
| 2 Gbit | ||
| DDR3 SDRAM | ||
| Tin-Silver-Copper | ||
| 260 | ||
| 1600 MHz | ||
| 146 mA | ||
| 2 Gbit | ||
| Surface Mount | ||
| 96 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1.5 V | ||
| 0 to 95 °C | ||
| 95 °C | ||
| 0 °C | ||
| 128M x 16 | ||
| 96F-BGA | ||
| 96 | ||
| 14 x 9 x 0.85 | ||
| Commercial | ||
| FBGA | ||
| 1.5 V | ||
| DDR3 SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | PROJECTED FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320024 |
| Schedule B: | 8542320060 |
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