MT29F2G08ABBGAH4-IT:G

MT29F2G08ABBGAH4-IT:G is a NAND flash memory. It includes an asynchronous data interface for high-performance I/O operations. This device uses a highly multiplexed 8bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND flash die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND flash die per chip enable signal.

• Open NAND flash interface (ONFI) 1.0-compliant, single-level cell (SLC) technology, feature set G
• Internal data move operations supported within the plane from which data is read
• Asynchronous I/O performance tRC/tWC: 20ns (3.3V), WP# signal: write protect entire device
• Array performance: read page: 115µs max (on-die ECC enabled) and 25µs max (on-die ECC disabled)
• RESET (FFh) required as first command after power-on, quality and reliability
• Advanced command set: program page cache mode, read page cache mode, block lock
• Operation status byte provides software method for detecting, write-protect status
• Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion
• 2Gb density, 8bit device width, SLC level, operating voltage range 1.8V (1.7 to 1.95V)
• 63-ball VFBGA package, industrial operating temperature range from -40 to 85°C