MT18KSF1G72HZ-1G6P1

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

• DDR3L functionality and operations supported as defined in the component data sheet
• 204-pin, small outline dual in-line memory module (SODIMM) with ECC
• Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, or PC3-6400
• 2GB (256 Meg x 72), 4GB (512 Meg x 72), 8GB (1 Gig x 72)
• VDD = 1.35V (1.283-1.45V)
• VDD = 1.5V (1.425-1.575V)
• Backward compatible to VDD = 1.5V ±0.075V
• VDDSPD = 3.0-3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Dual-rank
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus