MT16LSDF6464HY-13ED2

The MT16LSDF6464H is high-speed CMOS, dynamic random-access 256MB and 512MB unbuffered memory modules, organized in x64 configurations. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signal CK). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank, A0–A11 [256MB] or A0–A12 [512MB] select the device row). The address bits A0–A9 (for both 256MB and 512MB modules) registered coincident with the READ or WRITE command are used to select the starting device column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also enables the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. These modules are designed to operate in 3.3V, low power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, i

• PC100- and PC133-compliant, 144-pin, small outline, dual in-line memory module (SODIMM)
• Utilizes 100 MHz and 133 MHz SDRAM components
• Unbuffered
• 256MB (32 Meg x 64) and 512MB (64 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal SDRAM banks for hiding row access/ precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge and auto refresh modes
• Self refresh mode: standard and low-power
• 256MB module: 64ms, 4,096-cycle refresh (15.625µs refresh interval); 512MB: 64ms, 8,192-cycle refresh (7.81µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge connectors