EDY4016AABG-JD-F-ES-D

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• VDD = VDDQ = 1.2V } 60mV
• VPP = 2.5V, –125mV/+250mV
• 1.2V pseudoopen-drain I/O
• TC of 0°C to 95°C
  • 64ms, 8192-cycle refresh at 0°C to 85°C
  • 32ms at 85°C to 95°C
• 8 internal banks: 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write and read leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination (ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivit