EDFA232A1MA-GD-F-R

Mobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory device. LPDDR3 uses a double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus is used to transmit command, address, and bank information. Each command uses one clock cycle, during which command information is transferred on both the rising and falling edges of the clock. LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and eight corresponding nbit-wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

• Ultra-low-voltage core and I/O power supplies
• Frequency range
  • 800 MHz (data rate: 1600 Mb/s/pin)
• 8n prefetch DDR architecture
• 8 internal banks for concurrent operation
• Multiplexed, double data rate, command/address inputs; commands entered on each CK_t/CK_c edge
• Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c)
• Programmable READ and WRITE latencies (RL/WL)
• Burst length: 8
• Per-bank refresh for concurrent operation
• Auto temperature-compensated self refresh (ATCSR) by built-in temperature sensor
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock-stop capability
• On-die termination (ODT)
• Lead-free (RoHS-compliant) and halogen-free packaging