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SY89872UMG

Clock Buffer, Divider, Fanout 3.2 GHz to 2 Outputs, 2.375 V to 2.625 V, 16 Pins, QFN-EP

Manufacturer:Microchip
Product Category: Clock & Timing, Clock Buffers
Avnet Manufacturer Part #: SY89872UMG
Secondary Manufacturer Part#: SY89872UMG
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This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89872U includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank.Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF- AC reference is included for AC-coupled applications.The SY89872U is part of Micrel's high-speed Precision Edge® timing and distribution family. For 3.3V applications, consider the SY89873L. For applications that require an LVPECL output, consider the SY89872U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).

Guaranteed AC performance over temperature and voltage: >2GHz fMAX <750ps tPD (matched delay between banks) <15ps within-device skew <200ps rise/fall time Low jitter design 265 RMS phase jitter Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) Precision differential LVDS outputs Matched delay: all outputs have matched delay, independent of divider setting TTL/CMOS inputs for select and reset/disable Two output banks (matched delay) Bank A: Buffered copy of input clock (undivided) Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies 2.5V power supply Wide operating temperature range: -40°C to +85°C Available in 16-pin (3mm x 3mm) QFN package

Technical Attributes

Find Similar Parts

Description Value
Clock Divider, Fanout Buffer
QFN-EP
3200 MHz
3.2 GHz
CML, HSTL, LVDS, LVPECL
1
2
16
85 °C
-40 °C
LVDS
2.625 Vdc
2.375 Vdc

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: EAR99
HTSN: 8542390050
Schedule B: 8542390060
In Stock :  0
Additional inventory
Factory Lead Time: 49 Weeks
Price for: Each
Quantity:
Min:100  Mult:100  
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100+
$5.9823
200+
$5.93191
400+
$5.88099
800+
$5.8296
1600+
$5.77975