SY89321LMG-TR
Translator, 2 Input, 2.5 ns, 3 V to 3.6 V, 8 Pins, MLF-EP
- RoHS 10 Compliant
- Tariff Charges
The SY89321L is a differential LVPECL/CML/LVDSto-LVTTL translator requiring only a single +3.3V power. The SY89321L is functionally equivalent to the SY100EPT21L, but in an ultra-small 8-pin MLF® package that features a 70% smaller footprint. This ultra-small package and low skew single gate design make the SY89321L ideal for applications that require the translation of a clock or data signal where minimal space, low power and low cost are critical. VBB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output should be bypassed to VCC with 0.01µF capacitor. Under open input conditions, the /IN will be biased at a VCC/2 voltage level and the IN input will be pulled to ground. This condition will force the Q output low to provide added stability. The SY89321L is compatible with positive ECL 100k logic levels.
3.3V power supply 1.9ns typical propagation delay 275MHz fMAX Differential LVPECL/CML/LVDS inputs 24mA LVTTL outputs Flow-through pinouts Internal input resistors: pulldown on IN, pulldown and pullup on /IN Q output will default LOW with inputs open VBB output Available in ultra-small 8-pin MLF® (2mm x 2mm) package
Technical Attributes
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| Description | Value | |
|---|---|---|
| Gold over Nickel Palladium | ||
| LM | ||
| Level Translator | ||
| 260 °C | ||
| -3 mA | ||
| 24 mA | ||
| 2.5@3.3V ns | ||
| Surface Mount | ||
| MSL 2 - 1 year | ||
| 3.3000 V | ||
| -40 to 85 °C | ||
| 8MLF | ||
| 8 | ||
| 2 x 2 x 0.9 mm | ||
| 0 | ||
| MLF | ||
| LVPECL/CML/LVDS to LVTTL |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |