PIC18LF25J10-I/SP

PIC18LF25J10 offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price. The PIC18F45J10 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications All of the devices in the PIC18F45J10 family incorporate a range of features that can significantly reduce power consumption during operation Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements On-the-Fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized All of the devices in the PIC18F45J10 family offer three different oscillator options. These include: Two Crystal modes, using crystals or ceramic resonators Two External Clock modes INTRC source (approximately 31 kHz) Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator.

• Special Microcontroller Features:
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• On-Chip 2.5V Regulator
• 4x Phase Lock Loop (PLL) available for Crystal and Internal Oscillators
• Self-Programmable under Software Control
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture:
  • Optional extended instruction set designed to optimize re-entrant code
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
  • Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
• Power-Managed modes with Clock Switching:
  • Run: CPU on, peripherals on
  • Idle: CPU off, peripherals on
  • Sleep: CPU off, peripherals off
• Flexible Oscilla