PIC16LF84T-04/SO

The PIC16F8X devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set is used to achieve a very high performance level.

PIC16F8X microcontrollers typically achieve a 2:1 code compression and up to a 4:1 speed improvement (at 20 MHz) over other 8-bit microcontrollers in their class.

The PIC16F8X has up to 68 bytes of RAM, 64 bytes of Data EEPROM memory, and 13 I/O pins. A timer/counter is also available.

The PIC16CXX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake the chip from sleep through several external and internal interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.

The devices with Flash program memory allow the same device package to be used for prototyping and production. In-circuit re-programmability allows the code to be updated without the device being removed from the end application. This is useful in the development of many applications where the device may not be easily accessible, but the prototypes may require code updates. This is also useful for remote applications where the code may need to be updated (such as rate informatio

• High Performance RISC CPU Features:
• Only 35 single word instructions to learn
• All instructions single cycle except for program branches which are two-cycle
• Operating speed: DC
  • 10 MHz clock input DC
  • 400 ns instruction cycle
• 14-bit wide instructions
• 8-bit wide data path
• 15 special function hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
  • External RB0/INT pin
  • TMR0 timer overflow
  • PORTB<7:4> interrupt on change
  • Data EEPROM write complete
• 1000 erase/write cycles Flash program memory
• 10,000,000 erase/write cycles EEPROM data memory
• EEPROM Data Retention > 40 years Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
  • 25 mA sink max. per pin
  • 20 mA source max. per