PIC16F628-20/SO

The high performance of the PIC16F628 family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F628 uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional Von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single-word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches.

• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Brown-out Detect (BOD)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Multiplexed MCLR-pin
• Programmable weak pull-ups on PORTB
• Programmable code protection
• Low voltage programming
• Power saving SLEEP mode
• Selectable oscillator options - FLASH configuration bits for oscillator options - ER (External Resistor) oscillator
• Reduced part count - Dual speed INTRC
• Lower current consumption - EC External Clock input - XT Oscillator mode - HS Oscillator mode - LP Oscillator mode
• In-circuit Serial Programming™ (via two pins)
• Four user programmable ID locations CMOS Technology:
• Low power, high speed CMOS FLASH technology
• Fully static design
• Wide operating voltage range - PIC16F627 - 3.0V to 5.5V - PIC16F628 - 3.0V to 5.5V - PIC16LF627 - 2.0V to 5.5V - PI