PIC12F752-I/P

Program Memory Organization The PIC12F752/HV752 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F752/HV752. The Reset vector is at 0000h and the interrupt vector is at 0004h 2.2 Data Memory Organization The data memory is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-6Fh in Bank 0 are General Purpose Registers, implemented as static RAM. Register locations 70h-7Fh in Bank 0 are Common RAM and shared as the last 16 addresses in all Banks. All other RAM is unimplemented and returns ‘0’ when read. The RP<1:0> bits of the STATUS register are the bank select bits. RP1 RP0 0 0 ? Bank 0 is selected 0 1 ? Bank 1 is selected 1 0 ? Bank 2 is selected 1 1 ? Bank 3 is selected

• High-Performance RISC CPU:
• Only 35 Instructions to Learn:
  • All single-cycle instructions except branches
• Operating Speed:
  • DC – 20 MHz clock input
  • DC – 200 ns instruction cycle
• 1024 x 14 On-chip Flash Program Memory
• Self Read/Write Program Memory
• 64 x 8 General Purpose Registers (SRAM)
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Microcontroller Features:
• Precision Internal Oscillator:
  • Factory calibrated to ±1%, typical
  • Software selectable frequency: 8 MHz, 4 MHz, 1 MHz or 31 kHz
  • Software tunable
• Power-Saving Sleep mode
• Voltage Range (PIC12F752):
  • 2.0V to 5.5V
• Shunt Voltage Regulator (PIC12HV752)
  • 2.0V to user defined
  • 5-volt regulation
  • 1 mA to 50 mA shunt range
• Multiplexed Master Clear wit