PIC12F683-E/P

Program Memory Organization The PIC12F683 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h. Data Memory Organization The data memory is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 of the STATUS register is the bank select bit.

• High-Performance RISC CPU:
• Only 35 instructions to learn:
  • All single-cycle instructions except branches
• Operating speed:
  • DC – 20 MHz oscillator/clock input
  • DC – 200 ns instruction cycle
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Special Microcontroller Features:
• Precision Internal Oscillator:
  • Factory calibrated to ±1%, typical
  • Software selectable frequency range of 8 MHz to 125 kHz
  • Software tunable
  • Two-Speed Start-up mode
  • Crystal fail detect for critical applications
  • Clock mode switching during operation for power savings
• Power-Saving Sleep mode
• Wide operating voltage range (2.0V-5.5V)
• Industrial and Extended temperature range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Brown-out Rese