M1AFS600-2FG484I

The Fusion family, based on the highly successful ProASIC 3 and ProASIC3E flash FPGA architecture, has been designed as a high-performance, programmable, mixed signal platform. By combining an advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion devices dramatically simplify system design and, as a result, dramatically reduce overall system cost and board space. The devices in the Fusion family are categorized by FPGA core density. Each family member contains many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC), high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the user with a high level of flexibility and integration to support a wide variety of mixed signal applications. The flash memory block capacity ranges from 2 Mbits to 8 Mbits. The integrated 12-bit ADC supports up to 30 independently configurable input channels.

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Nonvolatile, Retains Program when Powered Off
• Instant On Single-Chip Solution
• 350 MHz System Performance
• 1 Kbit of Additional FlashROM
• Up to 12-Bit Resolution and up to 600 Ksps
• Internal 2.56 V or External Reference Voltage
• ADC: Up to 30 Scalable Analog Input Channels
• High-Voltage Input Tolerance: –10.5 V to +12 V
• Current Monitor and Temperature Monitor Blocks
• Internal 100 MHz RC Oscillator (accurate to 1%)
• Crystal Oscillator Support (32 KHz to 20 MHz)
• Programmable Real-Time Counter (RTC)
• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• Sleep and Standby Low-Power Modes
• ARM® Cortex-™M1 Enabled
• Designed in Partnership with Pigeon Point Systems
• ARM Cortex-M1 Enabled