LAN91C111-NS

The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications.

• Single Chip Ethernet Controller
• Dual Speed - 10/100 Mbps
• Fully Supports Full Duplex Switched Ethernet
• Supports Burst Data Transfer
• 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers
• Enhanced Power Management Features
• Optional Configuration via Serial EEPROM Interface
• Supports 8, 16 and 32 Bit CPU Accesses
• Internal 32 Bit Wide Data Path (Into Packet Buffer Memory)
• Built-in Transparent Arbitration for Slave Sequential Access Architecture
• Flat MMU Architecture with Symmetric Transmit and
• Receive Structures and Queues
• 3.3V Operation with 5V Tolerant IO Buffers (See Pin
• List Description for Additional Details)
• Single 25 MHz Reference Clock for Both PHY and
• MAC
• External 25Mhz-output pin for an external PHY
• supporting PHYs physical media.
• Low Power CMOS Design
• Supports Multiple Embedded Processor Host Interfaces
  • ARM