KSZ8995MAI

The KSZ8995MQX/RQX/FQX/ML is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost. Intended for cost sensitive 10/100Mbps five-port switch systems with low power consumption, on-chip termination, and internal core power controllers, it supports high-performance memory bandwidth and shared memory-based switch fabric with non-blocking configuration. Its extensive feature set includes power management, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four queue QoS prioritization, management interfaces, and MIB counters. The KSZ8995 family provides multiple CPU data interfaces to effectively address both current and emerging fast Ethernet applications when port 5 is configured to separate MAC5 with SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces. The KSZ8995 family offers three configurations, providing the flexibility to meet different requirements: - KSZ8995MQX/ML has 5 10/100Base-T/TX transceivers, 1 SW5-MII and 1 P5-MII interface - KSZ8895RQX has 5 10/100Base-T/TX transceivers, 1 SW5-RMII and 1 P5-RMII interface - KSZ8895FQX has 4 10/100Base-T/TX transceivers on Ports 1, 2, 3 and 5 (port 3 can be set to the fiber mode). 1 100Base-FX transceivers on Port 4. 1 SW5-MII and 1 P5-MII interface. All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode. KSZ8995MQX/RQX/FQX are 128-pin PQFP package. KSZ8995ML is 128-pin LQFP package.

Advanced Switch Features IEEE 802.1q VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs) Static MAC table supports up to 32 entries VLAN ID tag/untag options, per port basis Comprehensive Configuration Register Access Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers High-speed SPI (up to 25MHz) and I2C master Interface to all internal registers I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode QoS/CoS Packet Prioritization Support Per port, 802.1p and DiffServ-based 1/2/4-queue QoS prioritization selection Programmable weighted fair queuing for ratio control Integrated 5-Port 10/100 Ethernet Switch New generation switch with five MACs and five PHYs that are fully compliant with the IEEE 802.3u standard PHYs designed with patented enhanced mixed-signal technology Non-blocking switch fabric assures fast packet delivery by utilizing a 1K MAC address lookup table and