KSZ8851SNLI-TR

The KSZ8851M-series is a single-port controller chip with a non-PCI CPU interface and is available in 8/16-bit or 32-bit bus designs. The 48-pin LQFP KSZ8851-16MLL is for applications requiring high performance from single-port Ethernet Controller with 8-bit or 16-bit generic processor interface. The KSZ8851-16MLL offers a cost-effective solution for adding high-throughput Ethernet connectivity to traditional embedded systems. The KSZ8851-16MLL is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, an 8-bit or 16-bit generic host processor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851-16MLL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851-16MLL, the KSZ8851-16MLLI is also available. Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption. The KSZ8851-16MLL is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V or 3.3V VDD I/O. The device includes an extensive feature set that offers management information base (MIB) counters and CPU control/data interfaces with single shared data bus timing. The KSZ8851-16MLL includes unique cable diagnostics feature called LinkMD®. This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851-16MLL supports Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crosso

Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3u standards Designed for high performance and high throughput applications Supports 10BASE-T/100BASE-TX Supports IEEE 802.3x full-duplex flow control and halfduplex backpressure collision flow control Supports DMA-slave burst data read and write transfers Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking Supports IPv6 TCP/UDP/ICMP checksum generation and checking Automatic 32-bit CRC generation and checking Simple SRAM-like host interface easily connects to most common embedded MCUs Supports multiple data frames for transmit and receive without address bus and byte-enable signals Supports both Big- and Little-Endian processors Larger internal memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO Programmable low, high and overrun watermark for flow control in RX FIFO Shared data bus for Data, Address and Byte Enable Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V VDD