KSZ8851SNL-TR

The KSZ8851SNL is a single-chip Fast Ethernet controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Serial Peripheral Interface (SPI). The KSZ8851SNL is designed to enable an Ethernet network connectivity with any host micro-controller equipped with SPI interface. The KSZ8851SNL offers the most costeffective solution for adding high-throughput Ethernet link to traditional embedded systems with SPI interface. The KSZ8851SNL is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, SPI interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851SNL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851SNL, the KSZ8851SNLI is also available. Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption. The KSZ8851SNL is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V or 3.3V VDD I/O. The device includes an extensive feature set that offers management information base (MIB) counters and a fast SPI interface with clock speed up to 40MHz. The KSZ8851SNL includes unique cable diagnostics feature called LinkMD® . This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851SNL supports Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in applications.

Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3u standards SPI Interface with clock speeds up to 40MHz for high throughput applications Supports 10BASE-T/100BASE-TX Supports IEEE 802.3x full-duplex flow control and halfduplex backpressure collision flow control Supports RXQ and TXQ FIFO DMA for fast data read and write transfers Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking Supports IPv6 TCP/UDP/ICMP checksum generation and checking Automatic 32-bit CRC generation and checking Supports simple command and data phases in SPI cycle for RXQ/TXQ FIFO and registers read/write Supports multiple data frames for TXQ FIFO and RXQ FIFO without additional command phase Supports flexible Byte (8-bit), Word (16-bit) and Double word (32-bit) read/write access to internal registers Powerful and flexible address filtering scheme Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V VDD I/O Available in 32-pin (5mm x 5mm) MLF® package