KSZ8851-16MLL-TR

The KSZ8851 is a single-port embedded controller chip with 8/16/32-bit and SPI host interfaces. The device is pin compatible with Micrel's KSZ8841 and KSZ8842 product families.

The KSZ8851 integrates a Fast Ethernet MAC/PHY with an 8/16/32-bit generic host processor interface and SPI interface. The device has 18KB of internal buffer memory shared between the RXQ and TXQ. The buffer memory on the receive queue is 12KB while the buffer memory for the transmit queue is 6KB.

The KSZ8851 is designed with flexibility in mind. The device is designed using a low-power CMOS process which features programmable IO options of 1.8/2.5/3.3V. The KSZ8851 supports cable diagnostics feature LinkMD and Auto-MDIX. The LinkMD feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Hewlett Packard (HP) Auto-MDIX features eliminates the need to differentiate between straight or crossover cables.

The KSZ8851 is designed to be fully compliant with the IEEE 802.3 standards. The KSZ8851 is also available in industrial grade version.

• Single chip 10BASE-T/100BASE-TX Ethernet controller with IEEE802.3u support
• Supports IEEE 802.3x full-duplex flow control and half duplex backpressure collision flow control
• Single bus timing for register and data accesses
• Supports burst data transfers
• Flexible 8-bit, 16-bit, 32-bit generic host processor interfaces and SPI host interface
• Supports both Big
  • and Little-Endian processors
• Efficient architecture design with configurable host interrupt schemes to minimize host CPU overhead and utilization
• 18KB internal memory for RX/TX FIFO buffers - 12KB RXQ and 6KB TXQ
• Ability to transmit and receive frames up to 2000 bytes
• Supports TCP/UDP/ICMP/IPv4/IPv6 32-bit CRC checksum generation and checking
• Powerful and flexible address filtering scheme
• Support for loop back mode
• Wake-on-LAN functionality - Incorporates Magic Packet™, network link state, and wake-up frame techn