AX2000-1CQ352M

Axcelerator devices offer high performance at densities of up to two million equivalent system gates. Based upon the Microsemi AX architecture, Axcelerator has several system-level features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic.

• Single-Chip, Nonvolatile Solution
• Up to 100% Resource Utilization with 100% Pin Locking
• 1.5V Core Voltage for Low Power
• Footprint Compatible Packaging
• Flexible, Multi-Standard I/Os:
  • 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation
  • Bank-Selectable I/Os - 8 Banks per Chip
  • Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3V PCI-X
  • Differential I/O Standards: LVPECL and LVDS
  • Voltage-Referenced I/O Standards: GTL+, HSTL Class 1SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
  • Registered I/Os
  • Hot-Swap Compliant I/Os (except PCI)
  • Programmable Slew Rate and Drive Strength on Outputs
  • Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs
• Embedded Memory
  • Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18, x36 Organizations Available)
  • Independent, Width-Configurable Read and Write Ports
  • Programmable Embedded FIFO Control Logic