ATXMEGA64D3-AUR

AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughput many times faster than conventional single-accumulator or CISC based microcontrollers. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The ATxmega64D3 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast start-up from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode.

• High-performance, low-power AVR® XMEGA® 8/16-bit Microcontroller
• Nonvolatile program and data memories
  • 64Kbytes of in-system self-programmable flash
  • 4Kbytes boot
  • 2Kbytes EEPROM
  • 4Kbytes internal SRAM
• Peripheral features
  • Four-channel event system
  • Five 16-bit timer/counters
  • Four timer/counters with four output compare or input capture channels
  • One timer/counter with two output compare or input capture channels
  • High resolution extension on two timer/counters
  • Advanced waveform extension (Awe) on one timer/counter
  • Three USARTs with IrDA support for one USART
  • Two two-wire interfaces with dual address match (I2 C and SMBus compatible)
  • Two serial peripheral interfaces (SPIs)
  • CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator
  • 16-bit real time counter (RTC) with separate oscillator
  • One sixteen-channel, 12-bit, 300ksps Analog to Digi