ATXMEGA384C3-MH

The AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The Tax devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode.

• High-performance, low-power ® AVR® XMEGA® 8/16-bit Microcontroller
• Nonvolatile program and data memories
  • 384KBytes of in-system self-programmable flash
  • 8KBytes boot section
  • 4KBytes EEPROM
  • 32KBytes internal SRAM
• Peripheral features
  • Two -channel DMA controller
  • Four-channel event system
  • Five 16-bit timer/counters
  • Four timer/counters with four output compare or input capture channels
  • One timer/counter with two output compare or input capture channels
  • High resolution extension on two timer/counters
  • Advanced waveform extension (Awe) on one timer/counter
  • One USB device interface
  • USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
  • 32 Endpoints with full configuration flexibility
  • Three USARTs with IrDA support for one USART
  • Two two-wire interfaces with dual address match (I²C and SMBus compatible)
  • Two seria