ATXMEGA32A4-CU

The AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A1 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. offers a free Touch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers.

• High-performance, Low-power AVR 8/16-bit AVR XMEGA Microcontroller
• Non-volatile Program and Data Memories
  • 16K - 128K Bytes of In-System Self-Programmable Flash
  • 4K Boot Code Section with Independent Lock Bits
  • 1K - 2K Bytes EEPROM
  • 2K - 8K Bytes Internal SRAM
• Peripheral Features
  • Four-channel DMA Controller with support for external requests
  • Eight-channel Event System
  • Five 16-bit Timer/Counters
  • Three Timer/Counters with 4 Output Compare or Input Capture channels
  • Two Timer/Counters with 2 Output Compare or Input Capture channels
  • High-Resolution Extensions on all Timer/Counters
  • Advanced Waveform Extension on one Timer/Counter
  • Five USARTs
  • IrDA Extension on one USART
  • Two Two-Wire Interfaces with dual address match (I2 C and SMBus compatible)
  • Two SPIs (Serial Peripheral Interfaces) peripherals
  • AES and DES Crypto Engine
  • 16-bit R