ATXMEGA192A3U-MH

The AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA A3U devices provide the following features: in-system programmable flash with read-while write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable multilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); seven flexible, 16-bit timer/counters with compare and PWM channels; seven USARTs; two two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; three serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-channel, 12-bit ADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and presale; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip debug and programming.

• High-performance, low-power AVR® XMEGA® 8/16-bit Microcontroller
• Nonvolatile program and data memories
  • 192K Bytes of in-system self-programmable flash
  • 2K Bytes EEPROM
  • 16K Bytes internal SRAM
• Peripheral features
  • Four-channel DMA controller
  • Eight-channel event system
  • Seven 16-bit timer/counters
  • Four timer/counters with four output compare or input capture channels
  • Three timer/counters with two output compare or input capture channels
  • High resolution extension on all timer/counters
  • Advanced waveform extension (Awe) on one timer/counter ? One USB device interface
  • USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
  • 32 Endpoints with full configuration flexibility
  • Seven USARTs with IrDA support for one USART
  • Two two-wire interfaces with dual address match (I2C and SMBus compatible)
  • Three serial peripheral interfaces (SPI