ATXMEGA16A4-MHR

The Microchip AVR XMEGAA4 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A4 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MH--allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A4 devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 34 general purpose I/O lines, 16-bit Real Time Counter (RTC), five flexible 16-bit Timer/Counters with compare modes and PWM, five USARTs, two Two Wire Serial Interfaces (TWIs), two Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, one Twelve-channel, 12-bit ADC with optional differential input with programmable gain, one Two-channel 12-bit DAC, two analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available.

• High-performance, Low-power 8/16-bit Atmel® AVR® XMEGA™ Microcontroller
• Non-volatile Program and Data Memories
  • 16 KB - 128 KB of In-System Self-Programmable Flash
  • 4 KB - 8 KB Boot Code Section with Independent Lock Bits
  • 1 KB - 2 KB EEPROM
  • 2 KB - 8 KB Internal SRAM
• Peripheral Features
  • Four-channel DMA Controller with support for external requests
  • Eight-channel Event System
  • Five 16-bit Timer/Counters
  • Three Timer/Counters with 4 Output Compare or Input Capture channels
  • Two Timer/Counters with 2 Output Compare or Input Capture channels
  • High-Resolution Extensions on all Timer/Counters
  • Advanced Waveform Extension on one Timer/Counter
  • Five USARTs
  • IrDA Extension on one USART
  • Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
  • Two SPIs (Serial Peripheral Interfaces) peripherals
  • AES and DES Crypto Engine
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