ATTINY87-XU

The ATtiny87 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny87 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny87 provides the following features: 8K/16Kbyte of in-system programmable flash, 512 bytes EEPROM, 512 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed timer/counter, universal serial interface, a LIN controller, internal and external interrupts, a 11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, timer/counter, ADC, analog comparator, and interrupt system to continue functioning. The power-down mode saves the register contents, disabling all chip functions until the next interrupt or hardware reset. The ADC noise reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions The device is manufactured using high density non-volatile memory technology. The on-chip ISP flash allows the program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The Boot program can use any interface to download the application program in the Flash memory.

• High performance, low power AVR® 8-bit microcontroller
• Advanced RISC architecture
  • 123 powerful instructions – most single clock cycle execution
  • 32 x 8 general purpose working registers
  • Fully static operation
• Non-volatile program and data memories
  • 8K/16Kbyte of in-system programmable (ISP) program memory lash
  • endurance: 10,000 write/erase cycles
  • 512 bytes in-system programmable EEPROM
  • endurance: 100,000 write/erase cycles
  • 512 bytes internal SRAM
  • Programming lock for self-programming flash program and EEPROM data security
  • Low size LIN/UART software in-system programmable
• Peripheral features
  • LIN 2.1 and 1.3 controller or 8-bit UART (LIN 2.1 certified)
  • 8-bit asynchronous timer/counter0:
  • 10-bit clock presale
  • 1 Output compare or 8-bit PWM channel
  • 16-bit synchronous timer/counter1:
  • 10-bit clock presale
  • Ex