ATSAML21J17B-MUT

SMART SAM L21 is a series of Ultra low-power microcontrollers using the 32-bit ARM Cortex -M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and 40KB of SRAM. The SAM L21 devices operate at a maximum frequency of 48MHz and reach 2.46 CoreMark MHz They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The SAM L21 devices provide the following features: In-system programmable Flash, 16-channel direct memory access (DMA) controller, 12-channel Event System, programmable interrupt controller, up to 51 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and three Timer/Counters for Control (TCC) where each TC/TCC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and other control applications. Two TCC can operate in 24-bit mode, the third TCC can operate in 16-bit mode. The series provide one full-speed USB 2.0 embedded host and device interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN slave; up to twenty channel 1MSPS 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, two 12-bit 1MSPS DACs, two analog comparators with window mode, three independent cascadable OPAMPs supporting internal connection with others analo

• Processor
  • ARM Cortex-M0+ CPU running at up to 48MHz
  • Single-cycle hardware multiplier
  • Micro Trace Buffer
• Memories
  • 128KB in-system self-programmable Flash
  • 1/2/4/8KB Flash Read-While-Write section
  • 16KB SRAM Main Memory
  • 2/4/8/8KB SRAM Low power Memory
• System
  • Power-on reset (POR) and brown-out detection (BOD)
  • Internal and external clock options
  • External Interrupt Controller (EIC)
  • 16 external interrupts
  • One non-mask able interrupt
  • Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
• Low Power
  • Idle, Standby, Backup, and Off sleep modes
  • SleepWalking peripherals
  • Static and Dynamic Power Gating Architecture
  • Battery backup support
  • Two Performance Levels
  • Embedded Buck/LDO regulator supporting on-the-fly selection
• Peripherals
  • 16-channel Direc