ATSAMD21E16B-AU

The Microchip | SMART SAM D21 is a series of low-power microcontrollers using the 32-bit ARM Cortex -M0+ processor and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM D21 devices operate at a maximum frequency of 48MHz and reach 2.46 CoreMark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Microchip Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM D21 devices have two software-selectable sleep modes, idle and standby. In idle mode the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are stopped expect those selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug of application code.

• Processor
  • ARM Cortex-M0+ CPU running at up to 48MHz
  • Single-cycle hardware multiplier
  • Micro Trace Buffer (MTB)
• Memories
  • 32/64/128/256KB in-system self-programmable Flash
  • 4/8/16/32KB SRAM Memory
• System
  • Power-on reset (POR) and brown-out detection (BOD)
  • Internal and external clock options with 48MH- Digital Frequency Locked Loop (DFLL48M) and 48MH
  • to 96MH- Fractional Digital Phase Locked Loop (FDPLL96M)
  • External Interrupt Controller (EIC)
  • 16 external interrupts
  • One non-maskable interrupt
  • Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
• Low Power
  • Idle and standby sleep modes
  • SleepWalking peripherals
• Peripherals
  • 12-channel Direct Memory Access Controller (DMAC)
  • 12-channel Event System
  • Up to five 16-bit Timer/Counters (TC), configurable as either: