ATMEGA48V-10MMH

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Microchip ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

• High performance, low power Atmel® AVR® 8-bit microcontroller
• Advanced RISC architecture
  • 131 powerful instructions --most single clock cycle execution
  • 32 × 8 general purpose working registers
  • Fully static operation
  • Up to 20 MIPS throughput at 20MHz
  • On-chip 2-cycle multiplier
• High endurance non-volatile memory segments
  • 4/8/16 Kbytes of in-system self-programmable flash program memory
  • 256/512/512 bytes EEPROM
  • 512/1K/1Kbytes internal SRAM
  • Write/erase cyles: 10,000 flash/100,000 EEPROM
  • Data retention: 20 years at 85°C/100 years at 25°C(1)
  • Optional boot code section with independent lock bits
  • In-system programming by on-chip boot program
  • True read-while-write operation
  • Programming lock for software security
• QTouch® library support
  • Capacitive touch buttons, sliders and wheels
  • QTouch and QMatrix acquisition