ATMEGA168A-MUR

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers aredirectly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in onesingle instruction executed in one clock cycle. The resulting architecture is more code efficient while achievingthroughputs up to ten times faster than conventional CISC microcontrollers. The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2KbytesSRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters withcompare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire SerialInterface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), aprogrammable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. TheIdle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port,and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes theOscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, theasynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device issleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer andADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator isrunning while the rest of the device is sleeping. This allows very fast start-up combined with low powerconsumption. Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality intoAVR microcontrollers. The patented charge-transfer signal acquisition offers robus

• High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
• Advanced RISC Architecture
  • 131 Powerful Instructions – Most Single Clock Cycle Execution
  • 32 x 8 General Purpose Working Registers
  • Fully Static Operation
  • Up to 20 MIPS Throughput at 20MHz
  • On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
  • 4/8/16/32KBytes of In-System Self-Programmable Flash program memory
  • 256/512/512/1KBytes EEPROM
  • 512/1K/1K/2KBytes Internal SRAM
  • Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
  • Data retention: 20 years at 85?C/100 years at 25?C(1)
  • Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
  • Programming Lock for Software Security
• Atmel® QTouch® library support
  • Capacitive touch buttons, sliders and wheels
  • QTouch a