ATMEGA128A-AN

The Microchip AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega128A provides the following features: 128Kbytes of In-System Programmable Flash with Read- While-Write capabilities, 4Kbytes EEPROM, 4Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, one byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, one SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

• High-performance, Low-power Atmel AVR 8-bit Microcontroller
• Advanced RISC Architecture
  • 133 Powerful Instructions - Most Single-clock Cycle Execution
  • 32 × 8 General Purpose Working Registers + Peripheral Control Registers
  • Fully Static Operation
  • Up to 16MIPS Throughput at 16MHz
  • On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
  • 128Kbytes of In-System Self-programmable Flash program memory
  • 4Kbytes EEPROM
  • 4Kbytes Internal SRAM
  • Write/Erase cycles: 10,000 Flash/100,000 EEPROM
  • Data retention: 20 years at 85°C/100 years at 25°C(1)
  • Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
  • Up to 64 Kbytes Optional External Memory Space
  • Programming Lock for Software Security
  • SPI Interface for In-System Programming
• JTA