ATF750LVC-15SU
CPLD ATF750LVC Family 500 Gates 10 Macro Cells 50MHz CMOS Technology 3.3V 24-Pin SOIC
- RoHS 10 Compliant
- Tariff Charges
The “750” architecture is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. The ATF750LVC is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes proven electrically-erasable technology.
- 3.0V to 5.5V Operating Range
- Advanced, High-speed, Electrically-erasable Programmable Logic Device
- Superset of 22V10
- Enhanced Logic Flexibility
- Architecturally Compatible with ATV750B and ATV750 Software and Hardware
- D- or T-type Flip-flop
- Product Term or Direct Input Pin Clocking
- 10 ns Maximum Pin-to-pin Delay with 5V Operation
- 15 ns Maximum Pin-to-pin Delay with 3V Operation
- Highest Density Programmable Logic Available in 24-pin Package
- Advanced Electrically-erasable Technology
- Reprogrammable
- 100% Tested
- Increased Logic Flexibility
- 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
- Enhanced Output Logic Flexibility
- All 20 Flip-flops Feed Back Internally
- 10 Flip-flops are also Available as Outputs
- Programmable Pin-keeper Circuits
- Dual-in-line and Surface Mount Package in Standard Pinouts
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| SOIC | ||
| Surface Mount | ||
| 10 | ||
| 24 | ||
| 10 | ||
| 85 °C | ||
| -40 °C |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542310055 |
| Schedule B: | 8542310055 |