ATF1504ASL-25AU100

The Microchip ATF1504AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD) which utilizes the Microchip proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1504AS(L) enhanced routing switch matrices increases usable gate count and the odds of successful pin-locked design modifications. The ATF1504AS(L) has up to 68 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset, or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term which goes to a regional bus. Cascade logic between macrocells in the ATF1504AS(L) allows fast, efficient generation of complex logic functions. The ATF1504AS(L) contains four such logic chains; each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1504AS(L) macrocell, is flexible enough to support highly-complex logic functions operating at high speed. The macrocell consists of five sections: ? Product Terms and Product Term Select Multiplexer ? OR/XOR/CASCADE Logic ? Flip-flop ? Output Select and Enable ? Logic Array Inputs

• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device
  • 64 Macrocells ?
  • 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell ?
  • 44, 84, 100 Pins ?
  • 7.5ns Maximum Pin-to-pin Delay ?
  • Registered Operation up to 125MHz ?
  • Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell ?
  • D/T/Latch Configurable Flip-flops ?
  • Global and Individual Register Control Signals ?
  • Global and Individual Output Enable ?
  • Programmable Output Slew Rate ?
  • Programmable Output Open Collector Option
  • Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features ?
  • Automatic µA Standby for “L” Version ?
  • Pin-controlled 1mA Standby Mode ?
  • Programmable Pin-keeper Circuits on Inputs and I/Os ?
  • Reduced-power Feature