AT89LP51ID2-20AU

The AT89LP51ID2 is a low-power, high-performance CMOS 8-bit 8051 microcontroller with 64KB of In-System Programmable Flash program memory. The AT89LP51ID2 provide an additional 4KB of EEPROM for nonvolatile data storage. The devices are manufactured using high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set. The AT89LP51ID2 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles , forcing ins tructions to execute in 12, 24 or 48 clock cycles . In the AT89LP51ID2 CPU, standard instructions need only one to four clock cycles providing six to twelve times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reducing power consumption and EMI. The AT89LP51ID2 also includes a compatibility mode that will enable classic 12 clock per machine cycle operation for true timing compatibility with the AT89LP51ID2. The AT89LP51ID2 retains all of the standard features of the AT89LP51ID2, including: 64KB of In-System Programmable Flash program memory, 4KB of EEPROM (AT89LP51ID2 Only), 256 bytes of RAM, 2KB of expanded RAM, up to 40 I/O lines, three 16-bit timer/counters, a Programmable Counter Array, a programmable hardware watchdog timer, a keyboard interface, a full-duplex enhanced serial port, a serial peripheral interface (SPI), on-chip crystal oscillator, and a four-level, ten-vector interrupt system.

• 8-bit Microcontroller Compatible with 8051 Products
• Enhanced 8051 Architecture
  • Single Clock Cycle per Byte Fetch
  • 12 Clock per Machine Cycle Compatibility Mode
  • Up to 20 MIPS Throughput at 20 MHz Clock Frequency
  • Fully Static Operation: 0 Hz to 20 MHz
  • On-chip 2-cycle Hardware Multiplier
  • 16x16 Multiply Accumulate Unit
  • 256 x 8 Internal RAM
  • On-chip 2KB Expanded RAM (ERAM)
  • Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048 Bytes)
  • Dual Data Pointers
  • 4-level Interrupt Priority
• Nonvolatile Program and Data Memory
  • 64KB of In-System Programmable (ISP) Flash Program Memory
  • 4KB of EEPROM (AT89LP51ED2/ID2 Only)
  • 512-byte User Signature Array
  • Endurance: 10,000 Write/Erase Cycles
  • Serial Interface for Program Downloading
  • 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Boot loader