AT89C51RD2-SLSUM

AT89C51RD2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64-Kbyte Flash memory block for code and for data.The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial mode withthe ISP capability or with software. The programming voltage is internally generated from thestandard VCC pin. The AT89C51RD2/ED2 retains all of the features of the Microchip 80C52 with 256 bytes of internalRAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 provides2048 bytes of EEPROM for nonvolatile data storage.In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile serial channelthat facilitates multiprocessor communication (EUART) and a speed improvement mechanism(X2 Mode). The fully static design of the AT89C51RD2/ED2 allows to reduce system power consumption bybringing the clock frequency down to any value, including DC, without loss of data.The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8-bit clockprescaler for further reduction in power consumption. In the Idle mode the CPU is frozen whilethe peripherals and the interrupt system are still operating. In the Power-down mode the RAM issaved and all other functions are inoperative.The added features of the AT89C51RD2/ED2 make it more powerful for applications that needpulse width modulation, high speed I/O and counting capabilities such as alarms, motor control,corded phones, and smart card readers.

• 80C52 Compatible
  • 8051 Instruction Compatible
  • Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
  • Four 8-bit I/O Ports (44 Pins Version)
  • Three 16-bit Timer/Counters
  • 256 Bytes Scratch Pad RAM
  • 9 Interrupt Sources with 4 Priority Levels
• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
• ISP (In-System Programming) Using Standard VCC Power Supply
• 2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader
• High-speed Architecture
  • In Standard Mode:
• 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
  • In X2 mode (6 Clocks/machine cycle)
• 20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
• 64K Bytes On-chip Flash Program/Data