AT697F-KG-E

The AT697F is a highly integrated, high-performance 32-bit RISC embedded processor based on the SPARC V8 architecture. The implementation is based on the European Space Agency (ESA) LEON2 fault tolerant model. By executing powerful instructions in a single clock cycle, the AT697F achieves throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AT697F is designed to be used as a building block in computers for on-board embedded real-time applications. It brings up-to-date functionality and performance for space application. The AT697F only requires memory and application specific peripherals to be added to form a complete on-board computer. The AT697F contains an Integer Unit (IU), a Floating Point Unit (FPU), separate instruction and data caches, a hardware multiplier and divider, an interrupt controller, two 32- bit timers and a watchdog, two UARTs, a general-purpose I/O interfaces, a PCI Interface and a flexible memory controller. The design is highly testable with support from an embedded Debug Support Unit (DSU) with trace buffers and a JTAG interface for boundary scan. An idle mode holds the processor pipeline and allows Timer/Counter, Serial ports and Interrupt system to continue functioning. The processor is manufactured using the ATC18RHA CMOS process. It has been especially designed for space by implementing on-chip concurrent transient and permanent error detection and correction.

• SPARC V8 High Performance Low-power 32-bit Architecture
  • 8 Register Windows
• Advanced Architecture:
  • On-chip Amba Bus
  • 5 Stage Pipeline
  • 32 KB 4-way associative Instruction Cache
  • 16 KB 2-way associative Data Cache
• On-chip Peripherals:
  • Memory Interface
  • PROM Controller
  • SRAM Controller
  • SDRAM Controller
  • Timers: Two 32-bit Timers, Watchdog 32-bit Timer
  • Two 8-bit UARTs
  • Interrupt Controller with 8 External Programmable Inputs
  • 32 Parallel I/O Interface
  • 33MHz PCI Interface Compliant with 2.2 PCI Specification
• Integrated 32/64-bit IEEE 754 Floating-point Unit
• Fault Tolerance by Design
  • Full Triple Modular Redundancy (TMR)
  • EDAC Protection
  • Parity Protection
• Debug and Test Facilities
  • Debug Support Unit (DSU) for Trace and Debug
  • IEEE 1149.1 JTAG Interface
  • Four H