AT32UC3B164-AUT

The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 60 MHz AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3B incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access controller enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead transferring continuous and large data streams between modules within the MCU. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

• High Performance, Low Power 32-Bit AVR Microcontroller
  • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
  • Read-Modify-Write Instructions and Atomic Bit Manipulation
  • Performing up to 1.39 DMIPS / MHz
  • Up to 83 DMIPS Running at 60 MHz from Flash
  • Up to 46 DMIPS Running at 30 MHz from Flash
  • Memory Protection Unit
• Multi-hierarchy Bus System
  • High-Performance Data Transfers on Separate Buses for Increased Performance
  • 7 Peripheral DMA Channels Improves Speed for Peripheral Communication
• Internal High-Speed Flash
  • 64K Bytes Version
  • Single Cycle Access up to 30 MHz
  • Prefect Buffer Optimizing Instruction Execution at Maximum Speed
  • 4ms Programming Time and 8ms Full-Chip Erase Time
  • 100,000 Write Cycles, 15-year Data Retention Capability
  • Flash Security Locks and User Defined Configuration Area
• Internal High-Spe