AT24MAC602-MAHM-T

The AT24MAC602 provides 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) organized as 256 words of eight bits each and is accessed via an I2C-compatible (2-wire) serial interface. In addition, AT24MAC602 incorporates an easy and inexpensive method to obtain a globally unique MAC or EUI address (EUI-48 or EUI-64). AT24MAC402 is an EUI-48 compatible device that contains a 48-bit EUI address. The EUI-48 and EUI-64 addresses can be assigned as the actual physical address of a system hardware device or node or it can be assigned to a software instance. These addresses are factory programmed by and permanently write protected in an extended memory block located outside of the standard 2-Kbit bit memory array. the AT24MAC602 provides the value added feature of a factory-programmed, guaranteed unique 128-bit serial number located in the extended memory block (same area as the EUI address values). The serial number is factory-programmed and permanently write protected. This 128-bit serial number is compatible with all AT24CS, AT93CS, and AT25S family serial numbers, therefore, providing guaranteed unique serial numbers for any application that is also using Serial EEPROMs. The first-half of the AT24MAC602 incorporates a permanent and a reversible software write protection feature while a hardware write protect feature for the entire array is available via an external pin. The permanent software write protection is enabled by sending a special command to the device. This protection cannot be reversed once executed. However, the reversible software write protection can be reversed by sending and executing a special command. The hardware write protection is controlled by the WP pin state and can be used to protect the entire array regardless of whether or not the software write protection has been enabled. The software and hardware write protection features allow the user the flexibility to protect no portion of the memory, the firs

• Low-voltage Operation
  • 1.7V Minimum (VCC = 1.7V to 5.5V)
• Internally Organized as 256 x 8 (2K)
• I2C-compatible (2-wire) Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400kHz (1.7V) and 1MHz (2.5V, 5.0V) Compatibility
• Write Protect Pin for Hardware Data Protection of the Entire Array
• Permanent and Reversible Software Write Protection for the First-half of the Array
  • Software Procedure to Verify Write Protect Status
• 16-byte Page Write Modes
  • Partial Page Writes Allowed
• Self-timed Write Cycle (5ms max)
• High-reliability
  • Endurance: 1,000,000 Write Cycles
  • Data Retention: 100 Years
• Green Package Options (PB/Halide-free/RoHS Compliant)
  • 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 5-lead SOT23
• Die Sale Options: Wafer Form and Tape and