APA075-TQG100I

The ProASICPLUS family of devices, Actel’s secondgeneration family of flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to one million system gates, supported with up to 198 kbits of two-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of flash technology allows all functionality to be live at powerup. No external boot PROM is required to support device programming. While on-board security mechanisms prevent access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device’s architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a costeffective solution for applications in the networking, communications, computing, and avionics markets. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced flash-based 0.22 µm LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles. Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routin

• High Capacity - Commercial and Industrial
  • 75,000 to 1 Million System Gates
  • 27 K to 198 Kbits of Two-Port SRAM
  • 66 to 712 User I/Os
• High Capacity - Military
  • 300, 000 to 1 Million System Gates
  • 72 K to 198 Kbits of Two Port SRAM
  • 158 to 712 User I/Os
• Reprogrammable Flash Technology
  • 0.22 µm 4 LM Flash-Based CMOS Process
  • Live At Power-Up (LAPU) Level 0 Support
  • Single-Chip Solution
  • No Configuration Device Required
  • Retains Programmed Design during Power-Down/Up Cycles
  • Mil/Aero Devices Operate over Full Military Temperature Range
• Performance
  • 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military temperature)
  • Two Integrated PLLs
  • External System Performance up to 150 MHz
• Secure Programming
  • The Industry’s Most Effective Security Key (FlashLock®)
• Low Power
  • Low Impeda