AGLN250V2-VQ100

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-low power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO nano device is completely functional in the system. This allows the IGLOO nano device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low power, single-chip solution that is Instant On. The IGLOO nano device is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os. IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. Features such as smaller footprint packages designed with two-layer PCBs in mind, power consumption measured in nanoPower, Schmitt trigger, and bus hold (hold previous I/O state in Flash*Freeze mode) functionality make these devices ideal for depl

• Low Power
  • nanoPower Consumption—Industry’s Lowest Power
  • 1.2 V to 1.5 V Core Voltage Support for Low Power
  • Supports Single-Voltage System Operation
  • Low Power Active FPGA Operation
  • Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content
  • Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
• Small Footprint Packages
  • As Small as 3x3 mm in Size
• Wide Range of Features
  • 10,000 to 250,000 System Gates
  • Up to 36 kbits of True Dual-Port SRAM
  • Up to 71 User I/Os
• Reprogrammable Flash Technology
  • 130-nm, 7-Layer Metal, Flash-Based CMOS Process
  • Instant On Level 0 Support
  • Single-Chip Solution
  • Retains Programmed Design When Powered Off
  • 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance
• In-System Programming (ISP) and Security
  • ISP Using On